1. Field of the Invention
This invention relates to input/output (I/O) buffers used to drive signals upon, and receive signal from, transmission lines, and more particularly to the testing of impedance-controlled I/O buffers.
2. Description of the Relevant Art
Digital electronic devices typically communicate via electrical signals (e.g., voltage and/or current) driven upon electrical conductors (e.g., metal wires). As the operating frequencies (i.e., xe2x80x9cspeedsxe2x80x9d) of digital electronic devices increase, electrical conductors used to route signals between components (i.e., signal lines) begin to behave like transmission lines. Transmission lines have characteristic impedances. If the input impedance of a receiving device connected to a transmission line does not match the characteristic impedance of the transmission line, a portion of an incoming signal is reflected back toward a sending device. Such reflections cause the received signal to be distorted. If the distortion is great enough, the receiving device may erroneously interpret the logical value of the incoming signal.
Binary digital signals typically have a low voltage level associated with a logic low (i.e., a logic xe2x80x9c0xe2x80x9d), a high voltage level associated with a logic high (i.e., a logic xe2x80x9c1xe2x80x9d), xe2x80x9crise timesxe2x80x9d associated with transitions from the low voltage level to the high voltage level, and xe2x80x9cfall timesxe2x80x9d associated with transitions from the high voltage level to the low voltage level. A signal line behaves like a transmission line when the signal rise time (or signal fall time) is short with respect to the amount of time required for the signal to travel the length of the signal line (i.e., the propagation delay time of the signal line). As a general rule, a signal line begins to behave like a transmission line when the propagation delay time of the signal line is greater than about one-quarter of the signal rise time (or signal fall time).
Resistive xe2x80x9cterminationxe2x80x9d techniques are often applied to transmission lines, and signal lines long enough to behave like transmission lines, in order to reduce reflections and the resultant signal distortion. One or more electrically resistive elements may be inserted between each sending device and the signal line (i.e., transmission line) in order to cause the effective output impedances of the sending devices to more closely match the characteristic impedance of the transmission line. Similarly, one or more electrically resistive elements may be inserted between each receiving device and the transmission line in order to cause the effective input impedances of the receiving devices to more closely match the characteristic impedance of the transmission line.
Impedance-controlled buffers are often used to drive xe2x80x9cunterminatedxe2x80x9d transmission lines. In order to reduce signal reflections and distortion, the output impedance of an impedance-controlled I/O buffer connected to a transmission line is adjusted such that the output impedance is substantially equal to the characteristic impedance of the transmission line. Several factors may affect this impedance matching, including: (i) device variations due to variations in the fabrication process, (ii) supply voltage variations, and (iii) operating temperature variations. As a result, the output impedances of impedance-controlled I/O buffers are generally made variable and controllable by a one or more logic signals.
FIG. 1 is a block diagram of an exemplary impedance-controlled I/O buffer 10. I/O buffer 10 includes a pre-driver section 12 coupled to a driver section 14. Pre-driver section 12 receives an input data signal xe2x80x9cDATA_INxe2x80x9d at a data input terminal labeled xe2x80x9cDATA_INxe2x80x9d. Pre-driver section 12 also receives binary p-channel transistor enable signals xe2x80x9cEP1-EP5xe2x80x9d and n-channel transistor enable signals xe2x80x9cEN1-EN5xe2x80x9d (e.g., from a control unit). Pre-driver section 12 may include logic elements which produce p-channel transistor control signals xe2x80x9cP1-P5xe2x80x9d from enable signals EP1-EP5 and input data signal DATA_IN, and n-channel transistor control signals xe2x80x9cN1-N5xe2x80x9d from enable signals EN1-EN5 and input data signal DATA_IN. Driver section 14 receives p-channel transistor control signals P1-P5 and n-channel transistor control signals N1-N5 and produces an output data signal xe2x80x9cDATA_OUTxe2x80x9d at an data output terminal labeled xe2x80x9cDATA_OUTxe2x80x9d.
FIG. 2 is a circuit diagram of an exemplary embodiment of driver section 14. Driver section 14 includes five driver pairs 16-20. Each driver pair includes a p-channel transistor and an n-channel transistor connected in series between a first power supply voltage VDD and a second power supply voltage VSS, where VDD greater than VSS. Within each driver pair, a source region of the p-channel transistor is connected to VDD, a drain region of the p-channel transistor is connected to a drain region of the corresponding n-channel transistor at an output node, and a source region of the n-channel transistor is connected to VSS. The output nodes of all five driver pairs are connected to the DATA_OUT terminal of I/O buffer 10 as shown in FIG. 2.
Each driver pair of driver section 14 has an output electrical impedance which is largely resistive and inversely related to the current sourcing and sinking capability of the driver (i.e., the xe2x80x9cdrive strengthxe2x80x9d of the driver pair). The driver pairs may be configured such that the relative drive strengths double from one driver pair to the next. For example, a first driver pair 16 may have a base or reference drive strength, and a corresponding base or reference output impedance. A second driver pair 17 may have a drive strength twice the drive strength of driver pair 16, and an output impedance half that of driver pair 16. A third driver pair 18 may have a drive strength twice that of second driver pair 17 and 4 times the drive strength of first driver pair 16, and an output impedance one-fourth that of driver pair 16. A fourth driver pair 19 may have a drive strength twice that of third driver pair 18 and 8 times the drive strength of driver pair 16, and an output impedance one-eighth that of driver pair 16. A fifth driver pair 20 may have a drive strength twice that of fourth driver pair 19 and 16 times the drive strength of driver pair 16, and an output impedance one-sixteenth that of driver pair 16.
The transistors of driver section 14 need not be enabled in pairs, hence the separate enable signals EP1-EP5 and EN1-EN5. When the DATA_IN signal is a logic high (i.e., a logic xe2x80x981xe2x80x99), at least one p-channel transistor of driver section 14 is enabled by a corresponding enable signal EPx, where x is an integer between 1 and 5, and the output impedance xe2x80x9cZOUTxe2x80x9d of I/O buffer 10 is a parallel combination of the impedances of all of the enabled p-channel transistors. Similarly, when the DATA_IN signal is a logic low (i.e., a logic xe2x80x980xe2x80x99), at least one n-channel transistor of driver section 14 is enabled by a corresponding enable signal ENx, and the output impedance ZOUT of I/O buffer 10 is a parallel combination of all of the enabled n-channel transistors. Each transistor of driver section 14 has a different impedance inversely related to its current sourcing or sinking capability, thus the output impedance of I/O buffer 10 may be controlled by selectively asserting enable signals EP1-EP5 and EN1-EN5.
The DATA_OUT terminal of I/O buffer 10 may be connected to one end of a transmission line, and enable signals EP1-EP5 and EN1-EN5 may be selectively enabled (e.g., by a control unit) such that the output impedance ZOUT of I/O buffer 10 is substantially equal to the characteristic impedance of the transmission line. As a result, errors resulting from signal reflections and distortion may be reduced. Additionally, the values of enable signals EP1-EP5 and EN1-EN5 may be adjusted during operation to compensate for changes in the output impedance ZOUT of I/O buffer 10 due to variations in power supply voltages and/or variations in temperature.
When the values of enable signals EP1-EP5 and EN1-EN5 are changed during operation, data transmission errors may occur during xe2x80x9ctransition timesxe2x80x9d of enable signals EP1-EP5 and EN1-EN5 when enable signals EP1-EP5 and EN1-EN5 are changing state. The changing values of enable signals EP1-EP5 and EN1-EN5 may produce an xe2x80x9cintermediatexe2x80x9d value of the output impedance ZOUT of I/O buffer 10 which is different from the original value and the desired final value. Intermediate values of ZOUT greater than original values may result in data transmission errors.
For example, if the output impedance ZOUT of I/O buffer 10 is changed immediately following a DATA_OUT transition from logic xe2x80x9c1xe2x80x9d to logic xe2x80x9c0xe2x80x9d, and an intermediate value of ZOUT is greater than the original value, a positive error pulse may be generated at the DATA_OUT terminal. After a time period equal to the propagation delay of the transmission line, such a positive error pulse will arrive at the end of the transmission line opposite I/O buffer 10. The amplitude of the positive error pulse may be doubled at the end of the transmission line opposite I/O buffer 10. If the doubled amplitude of the positive error pulse exceeds the logic switchpoint level (e.g., Vdd/2), the positive error pulse may result in a false received logic xe2x80x9c1xe2x80x9d signal (i.e., a data transmission error). In order to reduce data transmission errors, enable signals EP1-EP5 and EN1-EN5 are always changed such that intermediate values of ZOUT are always less than original values. (See, for example, U.S. Pat. No. 5,751,161, xe2x80x9cUpdate Scheme for Impedance Controlled I/O Buffersxe2x80x9d, incorporated herein by reference in its entirety).
In a straightforward approach to testing I/O buffer 10, all 25 (32) possible combinations of EP1-EP5 would be required to verify the output impedance ZOUT of I/O buffer 10 when output data signal DATA_OUT is a logic xe2x80x9c1xe2x80x9d. Similarly, all 25 (32) possible combinations of EN1-EN5 would be required to verify the output impedance ZOUT of I/O buffer 10 when output data signal DATA_OUT is a logic xe2x80x9c0xe2x80x9d. Thus at least 2xc2x725 (64) separate tests are required to verify the output impedance ZOUT of I/O buffer 10. An integrated circuit may include, for example, hundreds of impedance-controlled I/O buffers 10. It is desirable to keep total testing time per integrated circuit to a minimum in order to produce as many integrated circuits as possible in a given amount of time. It would thus be beneficial to have a method and apparatus for testing a controlled-impedance I/O buffer in a manner which reduces the required test time.
A method and apparatus for testing an input/output (I/O) buffer in a highly efficient manner are disclosed. The I/O buffer includes multiple transistors coupled to a data output terminal. The method includes enabling a single one of the multiple transistors. A predetermined electrical voltage level is then forced upon the data output terminal, and a resultant electrical current flowing through the data output terminal (e.g., in a direction away from the I/O buffer) is measured. The measured electrical current is compared to predetermined minimum and maximum current values. A ratio of the measured electrical current to a reference current is computed, and the computed current ratio is compared to a predetermined minimum and maximum current ratio. The above steps may be repeated until each of the multiple transistors has been enabled.
The drive strength of a given transistor is a measure of the amount of electrical current the transistor causes to flow through the data output terminal when enabled. One or more of the multiple transistors has a drive strength which is less than all of the other transistors (i.e., a minimum drive strength). The reference current may be the amount of electrical current flowing through the data output terminal with the predetermined voltage level forced thereupon when the single enabled transistor has the minimum drive strength.
The I/O buffer may include multiple inputs for enabling the multiple transistors and a data input terminal. The enabling step may include applying signals to the inputs and the data input terminal such that the single one of the multiple transistors is enabled. A grouping of such signals applied to the inputs of the I/O buffer is termed herein an xe2x80x9cenable signal input pattern.xe2x80x9d
The multiple transistors may include several n-channel transistors coupled between a first power supply voltage and the data output terminal, and an equal number of p-channel transistors coupled between the data output terminal and a second power supply voltage. During testing, the data output terminal may forced to an electrical voltage level midway between the first and second voltage levels. For example, when the first voltage level (e.g., VDD) is a referenced to the second voltage level (e.g., VSS) the data output terminal may be forced to VDD/2.
The predetermined minimum electrical current value may be determined from a maximum output impedance value for the I/O buffer when the single one of the multiple transistors is enabled. Similarly, the predetermined maximum electrical current value may be determined from a minimum output impedance value for the I/O buffer when the single one of the multiple transistors is enabled.
One or more of the several n-channel transistors may have a reference (e.g., minimum) drive strength, and the other n-channel transistors may have a drive strength greater than the reference drive strength. The predetermined minimum and maximum current ratios used when a given n-channel transistor is the single transistor enabled may be based upon a ratio of the drive strength of the enabled n-channel transistor to the reference drive strength.
The apparatus for testing the I/O buffer includes a test unit adapted for coupling to the I/O buffer. The test unit includes a memory unit for storing an enable signal input pattern, and the corresponding minimum and maximum electrical current values and current ratios. During use, the test unit may apply the enable signal input pattern to the multiple inputs of the I/O buffer, force an electrical voltage of VDD/2 upon the data output terminal, measure a resultant electrical current flowing through the data output terminal, compare the measured electrical current to the minimum and maximum electrical current values, compute a ratio of the measured electrical current to the reference current, and compare the computed current ratio to the minimum and maximum current ratios.
The logic states of I/O buffer inputs may define impedance xe2x80x9cstatesxe2x80x9d of the I/O buffer. Impedance differences between such I/O buffer impedance states must be sufficient to reduce transmission errors. By testing the impedances of the individual transistors of an I/O buffer independently, the above described method and apparatus accomplish I/O buffer testing in a highly efficient manner.